1. Description of the Related Art
In recent years, image signal processing such as, digitizing demodulating image processing, compressing, and expanding the compressed image is disclosed for a satellite television modulation. As a processor programmably implementing this kind of processing, a processor having a single instruction stream/multiple data stream (SIMD) is well-known. The parallel processing method is disclosed in U.S Pat. No. 4,939,575, for example.
FIG. 18 shows a principle configuration of a related SIMD processor as described above. As shown in the figure, the processor includes data to be processed and a local storage 4 for storing the data resultant from the process. The local storage 4 stores a plurality of lines of pixel data to be processed. Data fetching unit (DFU) 5 receives a data item to be processed from among pixel data items retained in the local storage 4, and then retains the data item. Arithmetic and logical unit (ALU) 6 receives the pixel data being stored, performs predetermined operation for the data, and then supplies the data obtained by performing the operation to the local storage 4.
These local storage 4, DFU 5, and ALU 6 are divided into a plurality of processor elements 7-0 to 7-1079 in such a manner that a plurality of parallel operations can be simultaneously performed with each combination (with this example, 1,080 pieces) for each element. That is, the local storage 4, the DFU 5, and the ALU 6 are separated into local storage 4-0 to 4-1079, DFU 5-0 to DFU 5-1079, and ALU 6-0 to 6-1079 to constitute the local storage 4, DFU 5, and ALU 6. And, an operation is independently performed for each processor element. However, the operation performed by each processor element is common and its operation program to be run is directed to the ALU 6 via an instruction control bus 3 by the ALU SIMD controller 1. A program of the SIMD controller 1 is externally down-loaded.
FIG. 19 shows an example of configuration of the DFU 5-0 and ALU 6-0. Other DFUs 5-1 to 5-1079 and ALUs 7-1 to 7-1079, not shown, have the same configuration as the DFU 5-0 and ALU 6-0.
The DFU 5-0 receives 2-bit pixel data from the local storage 4-0 to cause them to be stored in a register 11 (register A) and a register 12 (register B), respectively. A register 13 (register C) was devised to retain carry-over data outputted by a full adder 22 (FA) included in the ALU 6-0.
Data retained in registers 11 to 13 of the DFU 5-0 is supplied to the full adder 22 of the ALU 6-0. The full adder 22 adds these three inputs and outputs a resultant sum and a carry-over to the selector 24. Among them, the carry-over is also supplied to the register 13 of the DFU 5-0.
The selector 24 selects either of two inputs transmitted from the full adder 22 to supply the input to a register 25 (a register W). The selection by the selector 7 is controlled by the SIMD controller 1 via an instruction control bus. The data retained in the register 25 is supplied to the local storage 4-0.
The full adder 22 adds the data retained in the registers 11 and 12 supplied from the local storage 4-0, and carry-over data generated in the previous calculation, outputting the added result data and carry-over data newly created to the selector 24. Additionally, the carry-over data is also supplied to the register 13 to be retained.
A SIMD controller 1 controls the selector 24 by way of an instruction control bus 3 to select, for example, a sum of the full adder 22 to retain the sum in a register 25. The operated result retained in the register 25 is supplied to the local storage 4-0.
The SIMD controller also controls the selector 24 so as to select the carry-over that the full adder 22 outputs and output it to a local storage 4-0 via register 25.
The operation described above is also performed in the other processors 7-1 to 7-1079 in a like manner.
FIG. 20 shows another principal configuration of a related SIMD control parallel processing method, the same symbols are assigned to portions corresponding to the same ones as in FIG. 21. In the configuration, the SIMD controller 1 controls the DFU 5 via the data control bus 2. And, DFU 5-0 and the ALU 6-0 are configured as shown in FIG. 21. The other DFU 5-1 to -1079, and ALU 6-0 to -1079, not shown, are configured identically to the DFU 5-0 and ALU 6-0, respectively.
The DFU 5-0 receives a 2-bit pixel data supplied from the local storage 4-0, and stores it in a register 11 (register A) and a register 12 (a register B), respectively. The selector 15 selects one data item among a predetermined value 1, data supplied to the register 11, and data retained in the register 14 to supply it to the register 14. It is directed by the SIMD controller 1 which input the selector 15 selects among these three inputs. A register 13 (register C) retains carry-over data outputted from the full adder (FA) included in ALU 6-0.
An AND circuit 20 of the ALU 6-0 performs logical al sum between data stored in the registers 11 and 14. An exclusive OR circuit 21 performs exclusive logical al OR between an output from the AND circuit 20, and data supplied by the SIMD controller 1 via the instruction control bus 3, and outputs the result obtained by the operation to a full adder 22. The full adder 22 is supplied data items each retained in the registers 12 and 13. The full adder 22 adds these three inputs, and outputs the sum and the carry-over resultant from the operation to a selector 24. Among them, the carry-over is supplied to the register 13 of the DFU 5-0.
The selector 23 selects either of the two data items supplied from the exclusive OR circuit 21 and the register 12 of the DFU 5-0 to output it to the selector 24.
The selector 24 selects either of the total three inputs of an input supplied from the selector 23 and two inputs from the full adder, and output it to a register 25 (register W). The selection of the selector 23 and the selector 24 are controlled by the SIMD controller via the instruction control bus. The data retained in the register 25 is supplied to the local storage 4-0.
For example, when the data stored in the local storage 4-0 is supplied to the ALU 6-0 as is, the SIMD controller 1 controls the selector 15 via the data control bus 2 so as to have a logical 1 stored therein to be selected to cause the register 14 to retain it. In addition, the selector 15 is caused to give a logical 0 to one input of the exclusive OR 21. As a result, a logical 1 retained in the register 14 is inputted to one side of the AND circuit 20, and thus data retained in the register 11 supplied by the local storage 4-0 passes the AND circuit 20 as it is and is inputted the full adder 22 via the exclusive OR circuit of the ALU 6-0. The full adder 22 adds data inputted from the exclusive OR circuit (data supplied from the register 11), data supplied from the local storage 4-0 and retained in the register 12, and carry-over data generated in the previous operation that is retained in the register 13, and output the result obtained by the addition and carry-over data newly generated to the selector 24. The carry-over is supplied to the register 13 also to be retained therein.
Additionally, the SIMD controller 1 controls the selector 24 via the instruction control bus 3 to cause the selector 24 to select, for example, a sum of the full adder 22 and then store it in the register 25. The result obtained by the operation that is stored in the register 25 is supplied to the local storage 4-0.
The SIMD controller 1 further can control the selector 24 to cause the selector 24 to select the carry-over outputted from the full adder 22 to output it to the local storage 4-0 via the register 25. Otherwise, the SIMD controller 1 enables the selector 23 to select either of two data items supplied by the exclusive OR circuit 21 or the register 12 and successively to select the data selected to supply it to the local storage 4-0 via register 25.
The SIMD controller 1, when it is desirous to reverse the logic of the data outputted from the AND circuit 20 and to supply it to the full adder 22, outputs a logical 1 to one input of the exclusive OR circuit 20. This causes the exclusive OR circuit 21 to output a logical 0 when a logical 1 is outputted from the AND circuit 20, and to output a logical 1 when a logical 0 is inputted from the AND circuit 20.
And, the SIMD controller 1, when it carries out a logical sum between newly inputted data and previous data, causes the selector 15 to re-select data retained in the register 14. This causes the register 11 to retain the next data, and thus current data and immediately previous data are inputted to the AND circuit 20 and performs its logical sum operation. The repetition of selecting the output of the register 14 by the selector 15 allows newly inputted data and past data to be logically operated.
The aforementioned operation is performed in the other processor elements 7-1 to -1079 in a like manner.
Japanese patent application number 07246627, 07290300, 08287173, and 08345359 disclose a similar image data processing system. Each of the above applications are owned by the assignee of the present invention and corresponding U.S. Applications are still pending.
As described above, in a conventional SIMD control processing method, each processor element 7-0 to 7-1079 is provided with an ALU (a full adder 22), respectively, thus making the configuration complicated. As a result, when this configuration is fabricated in an one-chip IC, an area occupied by the chip is not only enlarged, but also the IC is expensive. This was a remaining problem to be solved.
An embodiment according to the present invention will be described in detail hereinbelow.
The SIMD control parallel processing method described according to the first invention is characterized by including first retaining means (for example, a calculating unit 31 shown in FIG. 1) for retaining operated data specified by n-bit for each element, second retaining means (for example, an operation unit shown in FIG. 1) for previously retaining an operated result obtained by calculation performed in accordance with a predetermined equation, and selecting means for selecting the operated result corresponding to the one retained in the first retaining means for each element.
In the SIMD control parallel processing method according to the second invention, all previously calculated possible combinations of operated data specified by the n-bit data are previously retained. And, among operated result retained, a result corresponding to a calculated data is selected for each element.
Consequently, according to the SIMD control processing method and an operation method thereof according to the present invention, from among retained data obtained through operation, data corresponding to that resultant from the operation is selected for each element, thereby enabling a configuration to be simplified, smaller, and less costly.